1. Field of the Invention
The invention generally relates to power amplifiers (PAs) having cascode amplifier stages, and more specifically to PAs for high transmitted power communications when the devices need to withstand very large peak signal values.
2. Prior Art
Many of the modern wireless communication standards require very large power levels to be delivered by the power amplifier (PA) to an antenna. Some examples are cellular telephony with power up to +35 dBm at the PA output, wireless local area networks (WLAN), WiMax, etc. This results in very large peak voltages of the output of the active PA, which outputs may reach values of 10-15V.
Historically high power PAs have been dominated by bipolar implementations, e.g., SiGe heterojunction bipolar transistor (HBT), GaAs HBT, InGaP HBT, and the like. As shown in FIG. 1A, the active device 110 has a breakdown voltage (BV) of 15V or even more. It can deliver the high output power even in a single-ended configuration, which results in peak output voltages around 12V for a 35 dBm output power. The high cost of the exotic bipolar HBT process increases the overall cost of the system.
In contrast, the CMOS processes offer a low cost, a high available capacity of manufacturing and flexible production with multi-sources in a non-captive fab environment. However, the main drawback of the CMOS PA solutions is the much lower device breakdown voltage (BV), e.g., 2-4V, that requires more complex architectures to handle the required high output power. There are two main techniques used for the high power CMOS PAs as shown in FIG. 1B. On one hand the prior art uses segmented PA output stages which consist of connecting multiple similar stages, such as stages 130-1 and 130-n, in parallel, each of them operating only at a fraction of the output power and thus reducing dramatically the peak voltage seen by the active devices. The main drawback of this solution is the need for a large area output power combiner 140, which sums up the power provided by each stage. Such building blocks are usually built with large size transformers or transmission lines that increase the system cost.
A second method used is the differential output stages. For efficient classes of PAs the differential output drives the load symmetrically (plus and minus) approaching twice the drive duty cycle of a single ended PA. Each side of the differential circuit drives half of the load current. This reduces considerably the voltage stress on the active devices 132 and 134. Combining the segmentation with differential configurations allows the CMOS implementation of high power PAs. The main drawback of the differential configuration is the need for a large single-ended-to-differential and differential-to-single-ended converters.
Therefore, in view of the deficiencies of the prior art, it would be advantageous to provide a solution that overcomes these deficiencies.